This invention relates to high-density electronic packages, which are capable of incorporating more electronic capacity in a given space, or reducing the space required for a given amount of electronic capacity. Such packages are particularly useful as computer memories, control logic, arithmetic units, and the like.
The electronic density is obtained by means of a structure in which integrated circuit (IC) chips are stacked to form a three-dimensional structure. The stacked chip structure: (a) has atleast one interconnect plane which is adapted to be electrically connected to external circuitry; and (b) contains within its volume a very extensive electronic system. The term "interconnect plane" (which in related applications is referred to as an "access plane") signifies that electrical leads extend to that planar surface of the stacked chip structure.
A common assumption concerning such stacked IC chips is that the heat generated in the enclosed circuitry cannot be adequately dissipated.
In various prior applications and patents assigned to the assignee of this application, stacks of silicon IC chips have been proposed. One of those applications is U.S. application Ser. No. 856,835, filed Apr. 25, 1986 by the same inventor as the present application. That application discloses a three-dimensional module of stacked layers, or chips, each of which layers carries IC circuits whose leads extend to a common interconnect plane of the module. Electrically conductive bumps deposited on the access plane of the module are aligned with, and bonded to, electrically conductive bumps on a supporting substrate, thereby connecting the circuitry in the stacked layers to external circuitry.
Various limitations and deficiencies in the prior developments have led to the present invention. One such limitation is the fact that IC chips, such as memory devices, which are preferably obtained as standard (off-the-shelf) items from suppliers, must be modified to provide external leads only at one edge, instead of two edges, of each chip.
Perhaps the most critical problems encountered have been due to the electrically conductive properties of the material of the stacked chips, except for such materials as gallium arsenide and sapphire. Because the electrical leads at the interconnect plane must be insulated from the semiconductor material, it has been necessary to apply passivation material on the interconnect plane, and then to form T-shaped electrical connections by applying thin-film metallization to the interconnect plane.
These "T-connects" are fragile and therefore not very reliable. In the case of a silicon stack, the reliability of the "T-connects" depends to a large extent on the quality of the passivation layer. Another problem centers around the epoxy glue between layers, which is troublesome in several ways. Glue thickness variations, for example, can cause problems during certain processing steps, and the glue limits the stack's operating temperature to about 100.degree. C. It also limits the choice of material for the bonding bumps (to avoid degrading the glue and passivation due to high temperature). In addition to the "T-connect" problem and the glue problem, there is also a probem with flip-chip bonding (bump bonding) of the stacked chip module to a substrate. Flip-chip bonding has been less reliable as a method for making electrical interconnections than other methods, such as TAB bonding and wire bonding. In particular, it is not very practical in a mass production environment.
Another issue addressed by the present invention concerns heat transfer, particularly where the IC chips have high power requirements. Although silicon has reasonable heat-conducting properties, there is still the possibility of overheating problems in silicon stacks. Furthermore, the heat dissipation problem appears almost insurmountable (in stacked chip modules), if non-heat-conducting chips made of poor thermally-conducting material, such as gallium arsenide (GaAs), are used.
Such chips have certain advantages over silicon, including their ability to provide much higher speed electronic signals. However, the use of GaAs devices at higher speeds and temperatures, in the future can be expected to create packaging problems. As operating frequency increases into the gigahertz range, chip temperature increases and electrical/material properties begin to vary significantly. As a result, many other electrical properties are also affected; they include signal progagation delay, signal rise time, and characteristic impedances. Requirements for innovative denser packaging to help alleviate these problems have become critical. It is therefore obvious that special temperature considerations must be given to the packaging of GaAs devices to avoid degradation of their high speed performance.